Bipolar transistors are transistors used in high-frequency applications. The frequency response of a bipolar transistor is given by (1):
                              1                      2            ⁢            π            ⁢                                                  ⁢                          f              T                                      =                              τ            f                    +                                    (                                                R                  C                                +                                  R                  E                                            )                        ⁢                          C              BC                                +                                                                      C                  BE                                +                                  C                  BC                                                            I                C                                      ⁢                          U              T                                                          (        1        )            where fT is the transition frequency, τf is the transit time across the base, RC is the collector resistance, RE is the emitter resistance, CBC is the base-collector capacitance, CBE is the base-emitter capacitance, IC is the collector current and UT is the thermal voltage.
As the collector current IC increases, the term proportional to 1/IC becomes smaller and smaller. The principal proportion of the transition frequency fT is therefore given, besides the transit time τf, in particular by the collector resistance RC and the emitter resistance RE. In present transistors, the collector resistance RC is typically an order of magnitude greater than the emitter resistance RE. Therefore, the collector resistance is minimized to increase the frequency response of the transistors.
In order to obtain a low-impedance collector connection, a highly doped buried layer is used. This layer is produced at the beginning of the transistor fabrication steps. After this layer is fabricated, a semiconductor layer in which the emitter, base and collector zones are produced is grown epitaxially on the low-impedance layer. The highly doped buried layer is connected by means of a metallic collector contact and led to the surface of the bipolar transistor. This is described for example in U.S. Pat. No. 5,773,350 and DE 19958062.
In general, a collector contact is provided on only one side of the transistor. If the buried layer is connected not just on one side but also on the opposite side or even annularly around the entire transistor zone, lower collector resistances may be obtained. Such transistor configurations have a resistance with a magnitude about a half or a quarter that of a configuration having only a single collector contact, since the collector current can flow not just toward one side, but toward two or four sides.
FIG. 1 shows a schematic cross-sectional view of a known bipolar transistor 1 in which a buried layer 7 bounded by two insulation zones 11 is arranged in the semiconductor substrate 12. The insulation zones 11 are configured as deep trenches. The buried layer 7 is connected externally via a collector contact 6, which is led out electrically to the surface of the bipolar transistor 1. This enables the bipolar transistor 1 to be integrated into an integrated circuit.
The bipolar transistor 1 also contains a base contact 4 and an emitter contact 2 adjoining an emitter connection region 3. In order to reduce the base resistance, as illustrated in FIG. 1, a silicided base connection region 13 is provided on a base connection region 5. The base connection region 13 connects the base contact 4 to the base connection region 5. Such a bipolar transistor 1 is described in DE 199 58 062 by way of example.
The base zone 15 beneath the emitter connection region 3 may be silicon-germanium SiGe with a thickness of between 1 nm and 200 nm, typically 30 nm. The collector zone 14 is arranged beneath the base zone 15 and adjoins the buried layer 7. The buried layer 7 is provided with a collector contact 6 only on one side of the bipolar transistor 1 as shown in FIG. 1.
FIG. 2 schematically shows a plan view of a bipolar transistor in which the buried layer 7 is provided with a collector contact 6 on a single side. The base connection region 5 is connected by a base contact 4, and the emitter connection region 3 is connected by an emitter contact 2. In such a configuration, although the bipolar transistor 1 has a small area determined by the extent of the buried layer 7, the collector region (not illustrated here), on account of the relatively large sheet resistance of the buried layer 7, is connected by the collector contact 6 only on one side.
Smaller collector resistances can be obtained by the buried layer 7 being connected not just on one side, as in FIG. 2, but also on the opposite side, as shown schematically in a plan view in FIG. 3. The bipolar transistor 1 from FIG. 3 has a resistance with a magnitude about half that of the bipolar transistor 1 from FIG. 2.
However, it becomes clear that the area occupied by the buried layer 7 in FIG. 3 is larger than the buried layer 7 of the bipolar transistor from FIG. 2. The additionally required area of the buried layer 7 results from the width X1 of the collector contact 6, the distance X2 between the collector contact 6 and the base connection region 5, and an overhang X4 of the buried layer 7. The overhang X4 in FIG. 3 represents the distance between the collector contact 6 and the closest edge of the buried layer 7.
This additionally required area is given by the available photolithography and alignment tolerances. Typical contact hole widths in photolithography are presently 0.5 μm, for example, with alignment tolerances of 0.25 μm, so that overall the buried layer 7 is widened by about 1 μm if an additional collector contact 6 is provided.
Even lower sheet resistances of the buried layer 7 are obtained if, as shown schematically in FIG. 4, the collector contact 6 and the buried layer 7 are provided annularly around the base connection region 5. In this case, the collector current can flow on four sides, as a result of which the collector connection resistance is quartered. However, these enlarged collector contacts 6 lead to significantly enlarged dimensions of the bipolar transistor 1. In addition to increased production costs on account of the larger area required in the semiconductor substrate, the collector-substrate capacitance of the bipolar transistor 1 is also increased proportionally to the increasing area of the buried layer 7. This leads to a longer gate delay time of the transistor or an increased power consumption of integrated circuits.
Therefore, what transistor configuration has been used heretofore has depended on whether the transistor is designed for maximum transition frequency, as described with reference to FIG. 4, least space requirement, as described with reference to FIG. 2, or a compromise between the two, as described with reference to FIG. 3.
In summary, such transistors entail significant disadvantages. Firstly, the transistor dimensions are enlarged by the additional collector contact zones. This leads to higher production costs on account of the larger substrate area required. Secondly, the collector-substrate capacitance of the bipolar transistor is also increased proportionally to the increasing area of the buried layer. This in turn leads to adverse effects, such as a higher gate delay time or increased power consumption of integrated circuits.